Ferroelectric (FE) memory devices typically consist of a ferroelectric capacitor. The capacitor has ferroelectric material between two conductive electrodes. For simplicity, the capacitor often has a parallel plate configuration, but may take many different forms. FE materials have remanent polarization after application and removal of an electric field that allows them to function as non-volatile memory cells.
Prior art FIG. 1 shows the hysteresis curve 10 of electric field E versus the polarization P when a positive or negative electric field is applied across the ferroelectric capacitor where Ec is the coercive electric field and Pr is the remnant polarization. The capacitor is bistable, with two different polarization states possible when no electric field is applied. These can be used to represent values ‘0’ and ‘1.’ In the figure, the point 12 represents a ‘1’ and point 14 represents a ‘0.’ This assignment is arbitrary and the opposite assignment could also be made. Memory elements require circuits to read and write them. Writing is easily accomplished by applying a voltage across the capacitor, with a positive potential used to write one value and a negative potential to write the other.
Reading these types of memory cells presents many challenges. A common method applies a potential across the capacitor and uses a charge amplifier to measure the charge released by the capacitor during the transition. FIG. 2 shows a hysteresis curve 20 demonstrating how distinct memory states correspond to different amounts of charge. A voltage is applied across the capacitor and the charge released by the capacitor during transition. A large value may represent a ‘0’ and a small value may represent a ‘1.’ This process typically requires a precision sense amplifier.
FIG. 3 shows an example of a prior art read-out circuit 30 in which charge from the FE memory cell is integrated on the feedback capacitor of an operational amplifier. The example circuit 30 has a memory cell 32 connected to a word line WL, an operational amplifier 34, an inverting buffer 36 and an output terminal 38. The circuit also includes a reset switch 40 and a feedback capacitor 42. In this example, the charge from the ferroelectric memory cell 32 is integrated on the feedback capacitor 42 of the operational amplifier 34. The output of the amplifier is buffered, in this case inverting buffer 36, prior to being output at the terminal 38.
The use of an operational amplifier may be undesirable or impractical as it can add significant cost to the memory and is challenging to fabricate in many low-cost and large-area electronic technologies, such as those employing solution-processed thin film transistors (TFTs). These technologies have high variability, low yield, and low channel mobilities relative to conventional, vacuum-processed silicon electronics technologies. These characteristics of solution-processed TFTs result in amplifiers having high offset and gain mismatches and low gain, making them unsuitable for sensitive charge amplification or transduction.